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ITHEA Classification Structure > B. Hardware  > B.3 MEMORY STRUCTURES  > B.3.1 Semiconductor Memories
ITHEA Classification Structure > B. Hardware  > B.6 LOGIC DESIGN 
ITHEA Classification Structure > B. Hardware  > B.7 INTEGRATED CIRCUITS 
ITHEA Classification Structure > E. Data  > E.1 DATA STRUCTURES 
ITHEA Classification Structure > I. Computing Methodologies  > I.4 IMAGE PROCESSING AND COMPUTER VISION  > I.4.1 Digitization and Image Capture  
LARGE VLSI ARRAYS – POWER AND ARCHITECTURAL PERSPECTIVES
By: Adam Teman, Orly Yadid-Pecht and Alexander Fish (3199 reads)
Rating: (1.00/10)

Abstract: A novel approach to power reduction in VLSI arrays is proposed. This approach includes recognition of the similarities in architectures and power profiles of different types of arrays, adaptation of methods developed for one on others and component sharing when several arrays are embedded in the same system and mutually operated. Two types of arrays are discussed: Image Sensor pixel arrays and SRAM bitcell arrays. For both types of arrays, architectures and major sources of power consumption are presented and several examples of power reduction techniques are discussed. Similarities between the architectures and power components of the two types of arrays are displayed. A number of peripheral sharing techniques for systems employing both Image Sensors and SRAM arrays are proposed and discussed. Finally, a practical example of a smart image sensor with an embedded memory is given, using an Adaptive Bulk Biasing Control scheme. The peripheral sharing and power saving techniques used in this system are discussed. This example was implemented in a standard 90nm CMOS process and showed a 26% leakage reduction as compared to standard systems.

Keywords: VLSI Arrays, SRAM, Smart Image Sensors, Low Power, AB2C.

ACM Classification Keywords: B.3.1 Semiconductor Memories - SRAM, B.6 Logic Design – Memory Control and Access, B.7 Integrated Circuits – VLSI, E.1 Data Structures – Arrays, I.4.1 Digitization and Image Capture

Link:

LARGE VLSI ARRAYS – POWER AND ARCHITECTURAL PERSPECTIVES

Adam Teman, Orly Yadid-Pecht? and Alexander Fish

http://www.foibg.com/ijitk/ijitk-vol04/ijitk04-1-p08.pdf

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B.3.1 Semiconductor Memories
article: LARGE VLSI ARRAYS – POWER AND ARCHITECTURAL PERSPECTIVES · LARGE VLSI ARRAYS – POWER AND ARCHITECTURAL PERSPECTIVES ·
B.6 LOGIC DESIGN
article: LARGE VLSI ARRAYS – POWER AND ARCHITECTURAL PERSPECTIVES · IMPLEMENTATION OF A HEURISTIC METHOD OF DECOMPOSITION ... ·
B.7 INTEGRATED CIRCUITS
article: LARGE VLSI ARRAYS – POWER AND ARCHITECTURAL PERSPECTIVES ·
E.1 DATA STRUCTURES
article: MAIN DIFFERENCES BETWEEN MAP/REDUCE AND COLLECT/REPORT PARADIGMS · ЦЕЛОСТНОСТЬ ОБРАЗОВ: О МОДЕЛИРОВАНИИ СМЫСЛА И ПОНИМАНИЯ · LARGE VLSI ARRAYS – POWER AND ARCHITECTURAL PERSPECTIVES · CONSTRUCTION OF MORPHOSYNTACTIC DISTANCE ON SEMANTIC STRUCTURES · MEMBRANE STRUCTURE SIMPLIFICATION · SEMANTIC CONSTRUCTION OF UNIVOCAL LANGUAGE · КОГНИТИВНАЯ СЕМИОТИКА В ПРОЦЕССАХ ... · LOGARITHMIC DISTANCES IN GRAPHS · REPRESENTING TREE STRUCTURES BY NATURAL NUMBERS · BUILDING DATA WAREHOUSES USING NUMBERED INFORMATION SPACES ·
I.4.1 Digitization and Image Capture
article: LARGE VLSI ARRAYS – POWER AND ARCHITECTURAL PERSPECTIVES · JOINT STUDY OF VISUAL PERCEPTION MECHANISM AND COMPUTER VISION SYSTEMS THAT ... · ASTRONOMICAL PLATES SPECTRA EXTRACTION OBJECTIVES AND POSSIBLE SOLUTIONS ... ·
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