ITHEA International Scientific Society : OPTIMIZING PROGRAMMABLE LOGIC ARRAYS USING THE SIMULATED ANNEALING ALGORITHM

ITHEA Classification Structure > B. Hardware > B.6 LOGIC DESIGN > B.6.3 Design Aids
ITHEA Classification Structure > B. Hardware > B.7 INTEGRATED CIRCUITS > B.7.2 Design Aids

OPTIMIZING PROGRAMMABLE LOGIC ARRAYS USING THE SIMULATED ANNEALING ALGORITHM
By: Liudmila Cheremisinova, Irina Loginova (3331 reads)

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Abstract: In the paper the programmable logic array (PLA) topological optimization problem is dealt with using folding techniques. A PLA folding algorithm based on the method of simulated annealing is presented. A simulated-annealing PLA folding algorithm is presented for multiple unconstrained folding. Then, the algorithm is extended to handle constrained folding. In this way, simple folding is considered as a case of multiple constrained folding. Some experimental results of computer investigation of the suggested algorithms are given.

Keywords: design automation, area optimization, VLSI structure folding, simulated annealing.

ACM Classification Keywords: B.6.3 Logic Design: Design Aids – Optimization; B.7.2 Integrated circuits: Design Aids –Layout.

Link:

OPTIMIZING PROGRAMMABLE LOGIC ARRAYS USING THE SIMULATED ANNEALING ALGORITHM

Liudmila Cheremisinova, Irina Loginova

http://foibg.com/ijita/vol18/ijita18-4-p05.pdf