Abstract: The paper summarizes the authors methodology for solving the intractable combinatorial problems in physical design of electronic devices: VLSI, SOC, PCB and other. The Optimal Circuit Reduction (OCR) method has proved to be an efficient and effective tool to identify the hierarchical clusters’ circuit structure. The authors review the applicability of this method for solving of some problems, including hierarchical clustering, partitioning, packaging, and placement. Developed approach based on multilevel decomposition with the recursive use of global and local optimization algorithms at it every level for unique, not very large size subproblems. At every step we receive some initial solutions which are improved by optimization algorithms. Experiments confirm the efficiency of developed approaches. For some well-known test cases the optimal results were achieved for the first time, while for many other cases improved results were obtained.

Keywords: VLSI, SOC and PCB physical design, hierarchical clustering, partitioning, packaging, placement

ACM Classification Keywords: B.7.2 Design Aids

Link:

MACROMODELING FOR VLSI PHYSICAL DESIGN AUTOMATION PROBLEMS

Roman Bazylevych, Marek Pałasiński, Lubov Bazylevych

http://foibg.com/ibs_isc/ibs-23/ibs-23-p17.pdf