Abstract: The problem under consideration is to reduce the area of the layout of regular VLSI structures by means of their folding. A novel reformulation of the folding problem as the Boolean satisfiability problem solved with any standard SAT-solver is proposed. The method is developed that allows creating a Boolean equation presenting folding problem in CNF form.

Keywords: design automation, area optimization, VLSI structure folding.

ACM Classification Keywords: B.6.3 Logic Design: Design Aids – Optimization; B.7.2 Integrated circuits: Design Aids –Layout.

Link:

MULTIPLE FOLDING OF VLSI REGULAR STRUCTURE VIA BOOLEAN SATISFIABILITY

Liudmila Cheremisinova

http://foibg.com/ibs_isc/ibs-19/ibs-19-p51.pdf