Abstract: A verification task of proving the equivalence of two descriptions of the same device is examined for the case, when one of the descriptions is partially defined. In this case, the verification task is reduced to checking out whether logical descriptions are equivalent on the domain of the incompletely defined one. Simulation-based approach to solving this task for different vector forms of description representations is proposed. Fast Boolean computations over Boolean and ternary vectors having big sizes underlie the offered methods. Keywords: design automation, verification, Boolean computations, simulation. ACM Classification Keywords: B.6.2 Logic Design: Reliability and Testing; G.4 Mathematical Software: Verification; I.6.8 Simulation and Modeling: Types of Simulation – Parallel

Link:

SIMULATION-BASED APPROACH TO VERIFICATION OF LOGICAL DESCRIPTIONS WITH FUNCTIONAL INDETERMINACY

Liudmila Cheremisinova, Dmitry Novikov

http://www.foibg.com/ijita/vol15/ijita15-3-p03.pdf