Abstract: The reliability and the cost of electronic circuits are closely connected to the maximum power dissipated by them. Tools for evaluating the worst case power consumption of sequential circuits is becoming a primal concern for designers of low-power circuits. In the paper the task of estimation of peak sustainable power for CMOS synchronous sequential circuit is considered when its automaton description in the form of Finite State Machine (FSM) is available. The method is based on finding out the simple directed cycles of FSM state transition graph closely related with test sequences for simulating the sequential circuit for sustainable power estimation.

Keywords: low-power design, power consumption, CMOS circuits, peak power estimation.

ACM Classification Keywords: B.6.1 Logic design: Design Style – Sequential circuits; B.7.3 Integrated Circuits: Reliability and Testing – Test Generation

Link:

ESTIMATION OF PEAK SUSTAINABLE POWER CONSUMPTION FOR SEQUENTIAL CMOS CIRCUITS

Liudmila Cheremisinova, Arkadij Zakrevskij

http://www.foibg.com/ijita/vol21/ijita21-01-p10.pdf