Abstract: The authors present a hardware implementation of the codec for rank codes. Parameters of rank code are (8,4,5). Algorithmwas implemented on FPGA Spartan 3. Code rate is 1/2. The codec operates with elements from Galois field GF(28). The device can process informational data stream up to 77 MiB/s. Proposed results should help understanding rank code structure and simplify the problemof its application.

Keywords: rank codes, codec, error correction code, weak self-orthogonal bases, rankmetric, FPGA, key equation, Euclidean algorithm, fast computing.

ACMClassification Keywords: B.2.4 High-Speed? Arithmetic

MSC: 12Y05, 65Y20, 68W35.

Link:

HARDWARE IMPLEMENTATION OF RANK CODEC

Igor Sysoev,Ernst Gabidulin

http://www.foibg.com/ibs_isc/ibs-25/ibs-25-p19.pdf